In the design and manufacture of FET integrated circuits it is desirable to monitor the characteristics of the active channel of devices comprising the circuit. The present invention, useful in the integrated circuit art, is a gated transmission line model (GTLM) structure which provides a unique characterization device for accurately determining a variety of such parameters.
In the field effect transistor art, Transmission Line Model (TLM) measurements are a standard technique for the determination of the contact resistance and sheet resistance of the active layer.
In this invention the test structure has Schottky gates between the ohmic contacts of a conventional transmission line model (TLM) pattern, and the new test pattern is hereafter referred to as a gated-TLM or GTLM pattern. The gate lengths are different, one from the next, and the gate-to-ohmic separations are kept constant. With this structure the series resistance is nearly independent of the gate voltage and the channel resistance is modulatable by the gate voltage to provide an accurate determination of FET channel parameters.
At present there is no way to measure sheet resistance of the active layer of an enhancement-mode FET due to complete surface depletion. Since the GTLM structure can modulate the extent of this depletion, it offers a way to characterize enhancement-mode channels.
In addition to channel resistance, the parasitic source resistance is an important parameter to know, both for digital and (especially so) for low-noise analog FET applications.
A reference H. Fukui "Determination of the basis device parameters of a GaAs MESFET", Bell Sys. Tech. Journal, pp. 771-797, March 1979, shows a technique used to deduce source resistance Rs. The drain-to-source resistance Rds of a FET is measured at small Vds and plotted versus [(Vbi-Vgs)/Vpo]-0.5 where Vbi is built in junction voltage, Vgs is gate voltage and Vpo is pinch-off voltage. Vpo is arbitrarily adjusted to get a good linear fit and the Y-intercept of a least-squares regression to the data is used as 2Rs. The value of Rs determined in this way, however, varies significantly as Vpo is adjusted and therefore the method does not give accurate results. Also, the data is taken on a single FET so there is no way to average out any device peculiarities. Therefore this technique only provides an estimate for Rs.
The GTLM structure offers a means to deduce the source resistance with no parameter-fitting involved. In addition, the GTLM works equally well on planar, recessed-gate, and modulation-doped structures where other methods will fail due to undesirable current paths.
A reference K. Lee, et al, "Low field mobility in GaAs ion-implanted FETs," IEEE ED-31, No. 3, pp. 390-393, March 1984, shows a technique used to obtain mobility profiles. Measurements of low-field FET channel resistance and transconductance versus gate voltage are used together with a numerical solution of ##EQU1## to profile the mobility. This method requires a fitting parameter (Rs) to be adjusted in an iteration scheme with an assumed doping profile. Therefore the results will be an approximation. Also, the area of the device under test is generally too small to permit CV analysis. The GTLM structure deduces Rs automatically and therefore can use an iteration scheme to additionally deduce the doping profile.